1. Field of the Invention
The present invention relates to a module for mounting a driver IC (integrated circuit) constituting a drive circuit for driving display electrodes of a display device using a flat display panel and, in particular, relates to a new structure of the module for mounting the driver IC capable of supplying a stable large current having a predetermined peak to a display panel of the display device during operation of the display device.
The module for mounting the driver IC of this structure is typically applied to a display unit having a large-capacity flat display panel configured with a large-number of display cells having capacitive load characteristics, such as a plasma display panel (the whole of the plasma display unit including a plasma display panel and a peripheral circuit is generally referred to as xe2x80x9cPDPxe2x80x9d), an EL (electroluminescence) panel or a large-sized LCD (liquid crystal display) panel.
2. Description of the Related Art
Remarkable developments and progress in the flat display panels have been made recently. In particular, an AC (alternating current) plasma display panel of three-electrode surface discharge type, which is easy to increase the screen size and to display in color, is applied to a field of a large-capacity flat display panel, e.g, a large-sized color television, and has been put into practical use.
In this type of AC plasma display panel, voltage pulses are applied to two kinds of electrodes for sustaining the discharge alternately to sustain the discharge for luminous display. A period in which the discharge (lighting) occurs, due to the application of each of the voltage pulses, lasts several xcexcs (microseconds) after the application of each voltage pulse. Ions constituting positive charges generated by the discharge are accumulated over an insulating layer on the electrode which the negative voltage pulse is applied to. In a similar way, electrons constituting negative charges are accumulated over an insulating layer on the electrode which the positive voltage pulse is applied to.
Here, it is assumed that wall charges are generated by discharging with the voltage pulse (write pulse) of a high voltage (write voltage) at first and, subsequently, the voltage pulse having a voltage (sustain voltage) lower than the write pulse and also having the opposite polarity (sustain voltage pulse or sustain pulse). The voltage generated due to the wall charges which have been previously accumulated are superimposed on the sustain voltage to generate a sufficiently large voltage with respect to the discharge space. When such a large voltage exceeds the threshold value of the discharge voltage necessary for starting the discharge, the discharge is started. In other words, the cells in which write discharge has once occurred by means of the write pulse to generate the wall charges, subsequently continue to discharge by applying the sustain pulses to the two kinds of sustain discharge electrodes alternately with opposite polarities. This phenomenon is generally referred to as xe2x80x9cmemory effectxe2x80x9d or xe2x80x9cmemory drivexe2x80x9d. The AC plasma display panel is intended to realize the display utilizing this memory effect.
AC plasma display panels are classified into two types. One type is a two-electrode type of AC plasma display panel for carrying out the selective discharge (addressing discharge) and the sustain discharge with two kinds of electrodes. The other type is a three-electrode type of AC plasma display panel for carrying out the addressing discharge by utilizing a third kind of electrode, in addition to the sustain discharge with two kinds of electrodes. In the color plasma display panel for multi-gradation display, a phosphor formed in the cells is excited by ultraviolet rays generated due to the discharge. However, this phosphor has the disadvantage that it is relatively fragile against the bombardment of ions constituting the positive charges generated at the same time due to the discharge. The two-electrode type of the AC plasma display panel is configured so that ions directly collide with the phosphor, and therefore, the life of the phosphor is likely to become shortened. In order to avoid this disadvantage, the three-electrode type of AC plasma display panel, utilizing the surface discharge (generally referred to as xe2x80x9cAC plasma display panel of surface discharge typexe2x80x9d or xe2x80x9csurface discharge AC plasma display panelxe2x80x9d), is generally used.
In order to facilitate understanding of the problems concerning the conventional module for mounting the driver IC, an example of the conventional configuration of the module for mounting the driver IC applied to an ordinary plasma display panel will be explained, with reference to FIGS. 1 to 10 described later in xe2x80x9cBRIEF DESCRIPTION OF THE DRAWINGSxe2x80x9d.
A plan view showing a simplified model configuration of an ordinary AC plasma display panel of surface discharge type, is illustrated in FIG. 1. Further, a sectional view taken along the horizontal direction in FIG. 1, schematically showing the configuration of an ordinary AC plasma display panel of surface discharge type, is illustrated in FIG. 2.
As shown in FIGS. 1 and 2, a display panel 300 constituting an ordinary AC plasma display panel of surface discharge type is configured with two glass substrates 310 including a front glass substrate 310 and a rear glass substrate 320. The front glass substrate 310 has arranged thereon sustain electrodes (X1, X2, X3, . . . , Xj, . . . , Xn, where j is an arbitrary positive integer) constituted by a bus electrode and a transparent electrode and scanning electrodes (Y1, Y2, . . . , Yj, . . . , Yn).
Addressing electrodes (A1, A2, Ai, . . . , Am, where and i and m are arbitrary positive integers) are arranged in a form crossing at right angles to the sustain electrodes on the rear glass substrate 320. These three kinds of electrodes form each display cell 340 for generating the discharge light emission in a regions defined by the scanning electrode and the sustain electrode of the same number crossing at right angles to the addressing electrode. The sustain electrode (Xj), the scanning electrode (Yj) and the addressing electrode (such as Aixe2x88x921, Ai and Ai+1) are covered with a dielectric layer 350 for holding the wall charges. Further, a partition wall 330 for isolating the display cells from each other and a phosphor 360 for emitting light by means of ultraviolet rays generated due to the discharge are formed on the dielectric layer on the addressing electrode.
A block diagram showing the essential parts of the drive circuit for the AC plasma display panel of surface discharge type shown in FIGS. 1 and 2, is illustrated in FIG. 3.
As shown in FIG. 3, the surface discharge AC plasma display panel drive unit for activating the display panel 300 includes a control circuit 370 for generating a control signal for controlling the drive circuit of the AC plasma display panel of surface discharge type by interface signals (for example, a clock signal CLK, a data signal DATA, a vertical synchronous signal VSYNC and a horizontal synchronous signal HSYNC) input from an external source; and a sustain electrode circuit, a scanning electrode drive circuit and an addressing electrode drive circuit for driving the display electrodes of the display panel by the particular control signal. The sustain electrode drive circuit, the scanning electrode drive circuit and the addressing electrode drive circuit make up the essential parts of the drive circuit for the AC plasma display panel of a surface discharge type.
The sustain electrode drive circuit includes an X common driver 390 for generating the sustain pulse, the scanning electrode drive circuit includes a Y common driver 391 for generating the sustain pulse and a scanning circuit 392 for driving and scanning each scanning electrode independently. The addressing electrode drive circuit, on the other hand, includes an addressing circuit 380 for applying an addressing voltage pulse corresponding to the display data to each address electrode. The data signal DATA indicating the display data to be displayed on the display panel is temporarily stored in a frame memory 372 of a display data control unit 371 in the control circuit, and then supplied to the addressing circuit 380 in synchronism with the clock signal CLK. Further, the scanning circuit 392 is controlled by a scanning driver control unit 373 in the control circuit based on the vertical synchronous signal VSYNC. Furthermore, the X common driver 390 and the Y common driver 391 are controlled by a common driver control unit 374 in the control circuit based on the horizontal synchronous signal HSYNC.
A timing chart for explaining the operation of the drive circuit of FIG. 3, is illustrated in FIG. 4. This timing chart represents the essential points of a drive voltage waveform for image display on the display panel applied to each electrode in the operation of the drive circuit of FIG. 3, and primarily includes a write discharge period for the whole surface, an erase discharge period for the whole surface, an addressing discharge period and a sustain discharge period.
Among these periods, the drive period directly associated with the image display includes the addressing discharge period and the sustain discharge period. By selecting the pixels displayed during the addressing discharge period and emitting light from the selected pixels in the next sustain discharge period, a display of a predetermined brightness is accomplished.
During the addressing discharge period, the voltage of an intermediate voltage level xe2x88x92Vmy is applied to all the scanning electrodes (Y1 to Yn) at a time, after which the voltage level is switched to and applied as the scanning voltage pulse (scan pulse) of xe2x88x92Vy. In synchronism with the application of the scanning voltage pulse to each scanning electrode, each addressing electrode (A1 to Am) is impressed with the addressing voltage pulse of voltage level Va thereby to select the pixels on each scanning line.
In the next sustain discharge period, all the scanning electrodes (Y1 to Yn) and the X electrodes (X1 to Xn) are impressed alternately with the sustain voltage pulse of common voltage level +Vs, so that the previously selected pixels emit light. By this continuous application, the display of predetermined brightness is accomplished. Also, the density gradation can also be displayed by controlling the number of times in which light is emitted in combination with the series of basic operations of the drive voltage waveforms.
The write discharge period for the whole surface is for activating each display cell and holding a uniform display characteristic by applying a write voltage pulse of level Vwx to all the display cells on the whole panel surface, and is inserted at predetermined time intervals.
The erase discharge period for the whole surface, on the other hand, is for erasing the previous contents of display by applying a slope erase pulse of a peak voltage level Vey as an erase voltage pulse to all the display cells over the whole panel surface before starting a new addressing discharge operation and a new sustain discharge operation for image display.
A plan view showing the connection structure between the module for mounting the driver IC on the scanning electrode and the panel electrode of FIG. 4, is illustrated in FIG. 5. Further, a block diagram showing a circuit configuration of the module for mounting the driver IC of FIG. 5, is illustrated in FIG. 5. Further, a circuit diagram showing a circuit configuration of each driver IC chip in the module for mounting the driver IC, is illustrated in FIG. 7. FIGS. 5 to 7 show the manner in which the module for mounting the driver IC on the scanning electrode of the AC plasma display panel of surface discharge type including the three electrodes described above, is connected to the display panel, and also show a concrete circuit configuration of the module for mounting the driver IC.
The module for mounting the driver IC on the scanning electrode shown in FIGS. 5 and 6 represents a configuration example in which the display panel 300 has 480 scanning electrodes (Y1 to Y480). The driver IC chips 400 connected to these scanning electrodes each normally have an output of 64 bits, and therefore a total of eight driver chips are used. According to an embodiment of the present invention described later, the driver IC chips are distributed between two modules 401, 402 for mounting the driver IC, each of which includes four driver IC chips M1 to M4 mounted thereon. The input unit of these modules for mounting the driver IC includes input connectors 461, 462, respectively, while the output unit thereof has output terminals 471, 472 for connecting the scanning electrodes.
A concrete circuit in each driver IC chip is illustrated in FIG. 7. This circuit has an output circuit unit for outputting scanning electrode drive signals OUT1 to OUT64 corresponding to 64 bits.
These output circuit units are connected with a ground wiring GND for supplying the ground potential and a high power voltage power source wiring VH for supplying a high power source voltage through P-channel field effect transistors (hereinafter referred to as the P-channel FET) 406-1 to 406-64 and N-channel field effect transistors (hereinafter referred to as the N-channel FET) 407-1 to 407-64 of push-pull type in the last stage of the output portion. Further, diodes 408-1 to 408-64 are connected in opposite polarities between the source and the drain of the P-channel FETs 406-1 to 406-64, respectively. The cathodes of these diodes 408-1 to 408-64 are all connected to the high voltage power source wiring VH and operate so that the drive current is absorbed into the high voltage power source wiring. On the other hand, diodes 409-1 to 409-64 are connected in opposite polarities between the drain and the source of the N-channel FETs 407-1 to 407-64, respectively. The anodes of all the diodes 409-1 to 409-64 are also connected to the ground wiring GND, and operate so that the drive current flows into the output side from the ground wiring GND.
It should be noted that the ground wiring GND shown in FIGS. 6 and 7 is defined merely as the relative ground wiring formed in the two modules 401, 402 for mounting the driver IC, and does not always have an absolute ground potential. Conversely, since the voltage pulse for driving the display panel 300 is supplied from the Y common driver 391 to the ground wiring GND, the potential of the ground wiring GND varies greatly with respect to time (i.e., floating ground wiring GND).
Further, the circuit in the driver IC chip of FIG. 7 includes a logic circuit for controlling the P-channel FETS and the N-channel FETS of the push-pull type described above. This logic circuit includes N-channel FETs 405-1 to 405-64 for controlling the on/off operation of the P-channel FETs 406-1 to 406-64, respectively, through a pair of resistors R1-1 to R1-64, R2-1 to R2-64, respectively, inverters 404-1 to 404-64 for controlling the on/off operation of the N-channel FETs 407-1 to 407-64, and NAND gates 403-1 to 403-64 for applying a control signal to the N-channel FETs 405-1 to 405-64 and the inverters 404-1 to 404-64 based on a strobe signal STB. These circuits are operated by a low voltage power source VCC for logic application.
Further, the internal circuit of the driver IC chip of FIG. 7 includes a 64-bit shift register 411 for selecting the 64-bit output circuit unit, and a latch circuit 412 for temporarily holding the control signal output from the 64-bit shift register and transmitting it to the NAND gates 403-1 to 403-64. The control signal is configured with a clock signal CLK and a data signal DATA input to the 64-bit shift register 411, a latch signal LATCH input to the 64-bit latch circuit 412 and a strobe signal STB for controlling the logic circuits.
A sectional view showing the structure of a first example of the conventional module for mounting the driver IC, is illustrated in FIG. 8. The module for mounting the driver IC of this configuration is generally referred to as xe2x80x9cCOB (chip on board) structurexe2x80x9d.
The module for mounting the driver IC shown in FIG. 8 is constructed so that a driver IC chip 400 is mounted on a printed circuit board 430 of a rigid type. Further, in the module for mounting the IC driver described above, the pad terminal 410 on the driver IC chip is connected, by wire bonding, to a connecting terminal connected to input signal and power supply line wiring patterns 440 formed in each layer of the printed circuit board 430 of multilayer wiring type. Further, the input unit of the module for mounting the driver IC described above has an input connector 461 (or 462). This input connector 461 is connected with an input terminal wiring pattern 445 formed in the upper layer of the printed circuit board 430 of multilayer wiring type on the one hand and with the input signal and power supply line wiring patterns 440 of other layers of the printed circuit board 430, through conduction through holes 446, on the other hand.
Further, the voltage from the high voltage power source, the voltage from the low voltage power source, the ground potential and various signals are supplied from the input connector 461 and the input signal line and the power supply line wiring patterns 440 to the driver IC chip 400, through the corresponding pad terminal 410 on the driver IC chip. On the other hand, the output unit of the module for mounting the driver IC described above includes an output terminal connection pattern 450 formed in the upper layer of the printed circuit board 430. This connecting terminal 420 (i.e., the output terminal connection pattern 450) and the pad terminal 410 for outputting the driver signal from the driver IC chip 400 are directly connected and wired, by means of wire bonding, to each other.
Furthermore, the output terminal connection pattern 450 is led out to the end surface of the printed circuit board 430 and forms an output terminal connector. A flexible wiring board 480 having an output terminal wiring pattern 490 of the same shape as the output terminal connector is connected by thermal bonding to the output terminal connector, thereby forming one module for mounting the driver IC. A terminal which is to be connected to the display electrode of the display panel is arranged, at the forward end of the flexible wiring board 480. The output terminal unit 471 (or 472) having these terminals is used by being connected to the display electrode by means of a bonding technique such as thermocompression bonding.
A sectional view showing the structure of a second example of the conventional module for mounting the driver IC, is illustrated in FIG. 9. The module for mounting the driver IC having this configuration is generally referred to as xe2x80x9cCOM (chip on multiple board) structurexe2x80x9d.
Further, in the module for mounting the driver IC shown in FIG. 9, the printed board 510 of rigid type constituting a base is attached to the flexible wiring board board 530 formed with the output terminal wiring pattern 540 to a composite board 500 for the whole assembly.
Furthermore, in the module for mounting the driver IC shown in FIG. 9, the driver IC chip 400 is mounted on the printed circuit board 510 of a rigid type. Also, in the module for mounting the driver IC described above, the pad terminal 10 on the driver IC chip is connected and coupled, by wire bonding, with the connecting terminal connected to the input signal and power supply line wiring patterns 520 formed in each layer of the printed circuit board 510 of multilayer wiring type. Further, the input unit of the module for mounting the driver IC described above has an input connector 460, which is connected to the input terminal wiring pattern 515 formed in the upper layer of the printed circuit board 510 of multilayer wiring type on the one hand and to the input signal and power supply line wiring patterns 520 other layers of the printed circuit board 510, through the conduction through holes 516.
Further, the voltage from the high voltage power source, the voltage from the low voltage power source, the ground potential and various signals are supplied from the input connector 460 and the input signal and power supply line wiring patterns 520 to the driver IC chip 400, through the corresponding pad terminal 410 on the driver IC chip. On the other hand, the output unit of the module for mounting the driver IC described above has an output terminal wiring pattern 540 formed in the upper layer of the flexible wiring board 530 in the composite board. This output terminal wiring pattern 540 functions as a connecting terminal 420. This connecting terminal 420 (i.e., the output terminal wiring pattern 540) and the pad terminal 410 to which the drive signal is output from the driver IC chip 400 are directly connected and wired to each other by means of wire bonding.
Further, a terminal for connecting the display electrode of the display panel is arranged at the tip portion of the output terminal wiring pattern 540. These terminals are used by being connected to the display electrode by means of a bonding technique such as thermocompression bonding.
By the way, in both modules of FIGS. 8 and 9, a predetermined insulating film (such as a resist film or a cover lay film) is usually applied to the portion other than the terminals on the surface of each wiring board and the IC-mount, though not shown in FIGS. 8 and 9.
As shown in FIGS. 1 and 2, the internal structure of the display panel of an ordinary AC plasma display panel including the three-electrode surface discharge AC plasma display panel is such that all the display electrodes are covered with an insulating layer (dielectric layer), and a discharge gas is held in the space therebetween thereby to form a display cell. From the viewpoint of the drive circuit for driving these electrodes, therefore, the display electrodes have capacitive load characteristics. In the AC plasma display panel of surface discharge type shown in FIG. 2, for example, a capacitance Ca exists between the addressing electrodes and a capacitance Cg exists between the opposite electrodes, in addition to a capacitance Cs between the sustain electrode and the scanning electrode.
A timing chart showing the relationship between the drive voltage and the drive current of the scanning electrode of an ordinary AC plasma display panel of surface discharge type, is illustrated in FIG. 10.
The timing chart of FIG. 10 specifically shows the manner in which the drive current flowing in the scanning electrode changes upon application of the sustain pulse between the scanning electrode and the sustain electrode of the AC plasma display panel of surface discharge type. In synchronism with the timing of the rise of the sustain voltage pulse, the charge current and the gas discharge current flow in the form of peaks to the cell capacitance (i.e., the capacitance Cs between the sustain electrode and the scanning electrode and the capacitance Cg between the opposite electrodes), and in synchronism with the timing of the fall of the pulse, the discharge current flows in peaks from the cell capacitance. It should be noted that the capacitance Cs between the sustain electrode and the scanning electrode plays a primary role as the cell capacitance described above.
The peak current value of these drive currents, depending on the size of the display panel and the structure of the display cell, is generally 0.2 to 0.4 A per sustain electrode for the 42-inch display, and in terms of one driver IC chip on the scanning electrode having 64 outputs, the peak current is about 25 A at maximum. As a result, a maximum peak current larger than 90 A flows in one module for mounting the driver IC shown in FIG. 26.
Thus, the drive circuit is required to be constructed in such a manner as to be capable of supplying the above-mentioned peak current stably. First, it is necessary to use a driving element corresponding to such a peak current for the sustainer circuit including the X common driver and the Y common driver.
What is especially important is the configuration of the drive wiring system including the high voltage source wiring and the ground wiring leading from the sustainer circuit to the display panel. It is necessary to minimize the length of the wiring of the drive wiring system and to secure a sufficient wiring width and area for securing a low impedance line.
In the case in which the low impedance of the drive wiring system is difficult to realize, the peak current of the required magnitude cannot be supplied sufficiently as the drive voltage decreases, due to the impedance of the drive wiring system, even when the sustainer circuit has a sufficient driving capability. As a result, the luminous brightness of the discharge is reduced or the brightness variations occur so that the display quality of the plasma display panel deteriorates. At the same time, a sufficient margin of the drive voltage is difficult to secure, and display flickers or a luminous error (i.e., a luminous defect) occurs, thereby making the normal display operation impossible.
The number of display cells which are to be turned on among a plurality of the display cells arranged on each scanning line (display line) of the display panel is determined in accordance with the display data and generally varies from one scanning line to another. Specifically, each scanning line has a different load on the drive circuit. In the case in which the impedance of the drive wiring system is high, therefore, the value of the voltage drop of the drive voltage supplied to the display panel is varied from one display line to another. As a result, there occur some points in the display line in which the drive voltage of the required magnitude is not sufficiently supplied, thereby causing variations of the brightness on the display panel. In the case in which the drive voltage is increased in order to compensate for the drop of the drive voltage due to the impedance of the drive wiring system, on the other hand, the display cells which are not selected are liable to emit light, in addition to the display cells which are selected, and therefore the normal display operation becomes impossible.
Once the impedance of the ground wiring (or ground line) has increased, the flow of the high-frequency peak current constitutes noise in the drive circuit as a whole. As a result, a malfunction occurs in the drive circuit and the other circuits, thereby making it impossible to carry out the normal operation. Also, electromagnetic waves are radiated to have an adverse effect on the surrounding environment.
In such a drive wiring system, an especially disadvantageous point is the module for driving the display electrode connected directly to the display electrode of the display panel for mounting the driver IC connected directly to the display electrode of the display panel. It is important to attain a low impedance of the line of the drive wiring system for this portion of the module for mounting the driver IC.
The first example of the conventional module for mounting the driver IC as shown in FIG. 8 is configured so that various signals, including the clock signal, the latch signal and the strobe signal, are applied to the driver IC chip from the input connector 461 through the wiring pattern such as the input terminal wiring pattern 44 formed on the printed circuit board of a limited size. Therefore, a multilayer wiring is required using a multiplicity of conduction through holes in the printed circuit board. Specifically, the input wiring system utilizing the above-mentioned multilayer wiring uses a plurality of conduction through holes, and therefore, drive wiring systems including the high voltage power source wiring and the ground wiring or the like cross over the input wiring system for wiring. In the output wiring system for the module for mounting the driver IC, on the other hand, the pad terminal 410 and the output terminal for the output of the driver IC chip are connected with each other, through the output terminal connection pattern 450 on the printed circuit board. For this reason, the width and area of the drive wiring system are limited by an amount equivalent to the output terminal connection pattern and the conduction through holes. It is therefore difficult to realize a sufficiently low impedance for the drive wiring system.
On the other hand, in a second example of the conventional module for mounting the driver IC as shown in FIG. 9, a flexible wiring board 530 formed with the output terminal wiring pattern 540 of the output wiring system and the printed circuit board 500 are attached to each other. The output pad terminal of the driver IC chip 400 thus is directly connected to the output terminal wiring pattern by wire bonding. As a result, the output wiring system ceases to affect the drive wiring system. As compared with the first example described above, therefore, the width and area of the drive wiring system can be somewhat increased. Nevertheless, the input wiring system for the second example of the module for mounting the driver IC, similar to the first example, is wired by crossing the drive wiring system including the high voltage power source wiring and the ground wiring. Therefore, the width and area of the drive wiring system are still limited by an amount equivalent to the conduction through holes.
As a technique related to the conventional module for mounting the driver IC, Japanese Unexamined Patent Publication No. 10-215038 discloses a configuration of a composite circuit board including a flexible circuit board having a wiring pattern for drive circuitry for display in which an IC can be mounted with a power bus bar and a ground bus bar integratedly coupled on a part or the back of the flexible circuit board. In this composite circuit board, the drive wiring system including the power bus bar and the ground bus bar seem to be isolated from the input wiring system and the output wiring system, similar to the present invention. In this case, however, the wiring of the drive wiring system including the power bus bar and the ground bus bar is connected to the display drive IC, through the wiring pattern in the flexible circuit board, and therefore, is affected by the input wiring system and the output wiring system.
As another technique related to the conventional module for mounting the driver ID, Japanese Unexamined Patent Publication No. 5-198603 (registered as U.S. Pat. No. 2,803,699 on Jul. 17, 1998) discloses an IC chip mounting structure comprising a first board for mounting the IC chip and a flexible second board, wherein a driving wiring system including a high voltage power source wiring and a ground wiring is formed on the first board and an output wiring system is formed on the second board. In this mounting structure, the input wiring system is also considered to be formed on the first substrate, and therefore, like the prior art shown in FIGS. 8 and 9, the input wiring system is wired by crossing the drive wiring system. As a result, the width and area of the drive wiring system are still limited.
The present invention has been developed in view of the above-mentioned problems, and the object thereof is to provide a module for mounting the driver IC which is capable of realizing a drive wiring system of low impedance easily by minimizing the impedance of the drive wiring system of the module for the driver IC used in a flat display panel.
In order to achieve the object described above, according to the present invention, there is provided a module for mounting the driver IC comprising a driver IC chip for driving the display electrode of a flat display panel, and a wiring board for electrically connecting the driver IC chip. The module for mounting the driver IC comprises at least a first wiring unit formed with a drive power source system wiring for supplying a power source voltage input to the driver IC chip for driving the flat display panel; a second wiring unit formed with a control system wiring for supplying signals input to the driver IC chip for controlling the driver IC chip; and a third wiring unit formed with an output terminal wiring taken out from the driver IC chip and connected to the display electrode of the flat display panel.
The module for mounting the driver IC according to the present invention is divided into a first wiring unit formed with a drive voltage system wiring (i.e., a drive wiring system) for supplying a power source voltage for driving the flat display panel, a second wiring unit formed with a control system wiring (i.e., an input wiring system) for supplying various signals for controlling the driver IC chip, and a third wiring unit formed with an output terminal wiring (i.e., an output wiring system). Therefore, the input wiring system can be wired without crossing the drive wiring system, and a sufficient wiring space can be secured in the drive wiring system of the module for mounting the driver IC. As a result, it is possible to realize a module for mounting the driver IC in which the line impedance of the drive wiring system of the display panel is suppressed to a relatively low value.
With this module configuration according to the present invention described above, a sufficient peak current can be supplied to the display panel, and therefore, a sufficient brightness and stable display characteristics can be obtained. Also, a sufficient operating margin is secured for a normal display operation.
Further, in a module for mounting the driver IC according to the present invention, a display unit can be realized in which noises are suppressed at the time of operation of the flat display panel and a stable control operation can be performed.